Verification

Verification has become the major part of embedded design work. The session goes in detail on verifying device drivers against a virtual model of the custom hardware and a highly effective functional test of a SoC design.

Presentations will be made by:

Jakob Engblom Virtutec

“Verifying Software Drivers for Custom Hardware”


Many embedded systems contain application-specific custom hardware units. With each custom hardware unit comes the need to write device driver software. Device drivers tend to be hard to write and hard to test, and often contain subtle input- and timing-dependent bugs. 

Constrained random testing techniques and metric-driven verification has proven very useful in hardware verification. We have applied these techniques to embedded software by using a virtual platform to run the target software, operating system, and device drivers against a virtual model of the custom hardware. The virtual platform offers repeatable execution, control over time,
and the ability to inject hardware states, change hardware timing, and inject faults.

In the enviroment we have developed, driver software is exercised by varying calling sequences, input values, and hardware parameter settings according to
bounds and plans set up by verification engineers.  The net result is that driver software is tested in more depth and breadth than with manual testing, especially considering corner cases, the extremes of hardware behavior, and combinations of input values.

The Cadence ISX tool provides feedback on value coverage, behavior coverage, and lets users plan and execute their tests. Virtutech Simics provides a controlled execution environment for software, with a complete and extensible target hardware model. 
 

Jakob Engblom is a Technical Marketing Manager at Virtutech in Stockholm, Sweden. He holds an MSc in Computer Science and a PhD in Computer Systems from Uppsala University. He has a background in computer science, real-time systems, compiler technology, embedded software development, and computer simulation technology.
He has published more than 40 scientific papers, and has a blog at
http://jakob.engblom.se.

Alain Gonier, Mentor Graphics

”Verification and Debug of Multi-Core SoCs”

Leveraging a sign-off processor model to drive functional tests into a SoC is a highly effective method of block and chip level verification. But debug tools for processor models at RTL level are primitive at best and speed is dramatically reduced compared to a full SW environment, limiting the benefit of processor driven test. Multi-core designs compound the problem of limited debug visibility and speed. Isolating the cause of test failures can be simple and fast with the right tool. Mentor HW-SW coverification tool suite provides a rich source-level debug environment for RTL simulation as well as improvement in speed. This session looks at the challenges of debugging multi-core simulations, and demonstrates Mentor tool suite’s ability to simplify the task.

Alain Gonier, European Product Specialist, SoC Verification Group

Alain Gonier Joined Mentor in 1998, his previous position was as Software Engineer in the Automotive industry writing and verifying embedded SW for dashboards. Through 7 years in Mentor Consulting, Alain worked with major European electronic companies on-site across Europe - including Nokia, Ericsson, Texas Instruments, Philips/NXP, ST, helping them specify and implement best-in-class verification methodology using leading-edge tools. Since 2006, Alain has been working with the European Specialist Group helping adoption of Mentor Functional Verification tools & Methodology in Europe. His day to day job is to visit customers to understand their needs and propose appropriate solutions to improve their verification flow.